


Hence there is no current into the base of Q2 and making it into cur-off. The collector of Q2 is HIGH and turns Q3 into saturation. Since Q3 acts as a emitter follower, by providing a low impedance path from Vcc to the output, making the output into HIGH. At the same time, the emitter of Q2 is at ground potential, keeping Q4 OFF. When A and B are high, the two input base emitter junctions of Q1 are reverse biased and its base collector junction is forward biased.

This permits current through R1 and the base collector junction of Q1 into the base of Q2, thus driving Q2 into saturation. As a result Q4 is turned ON by Q2, and producing LOW output which is near ground potential. At the same time, the collector of Q2 is sufficiently at LOW voltage level to keep Q3 OFF. It is possible in TTL gates the charging of output capacitance without corresponding increase in power dissipation with the help of an output circuit arrangement referred to as an active pull-up or totem-pole output.

If we look at the circuit, we observe that when the transistor is saturated, it presents a very low effective resistance to ground. The problem arises when the output is high and the pull-up resistor is too large. Ideally we would like to have a very low resistance pull-up when the output is high, but a very high pull-up resistance when the output is low. In this way, we could get quick charging and very low power dissipation. The totem-pole output stage for TTL, shown in Figure. Low-power Schottky TTL designed as 74LS or 54LSĪdvanced low-power Schottky TTL designed as 74ALS or 54ALSĪdvanced Schottky TTL designed as 74AS or 54ASĪn alphabetic code preceding this indicates the name of the manufacturer. TOTEM POLE OUTPUT FOR TTL LOGIC FAMILIES CODE TOTEM POLE OUTPUT FOR TTL LOGIC FAMILIES CODE.
